Efficient Memory Controller Architectures and their Integration in Transprecision Compute Platforms
Content of the lecture:
In this talk, I will explain the main building blocks of DRAM (DDR) memory controllers and how they impact the usage and utilization of DRAMs. Nowadays, the focus moves away from compute centric to memory centric processing. Thus, we will discuss in this lecture how we can utilize the available memory resources more efficiently and which optimizations and use cases are sensible. Further, transprecision techniques used in our DDR controller design are presented and discussed.
He received the Ph.D. degree in electrical engineering from the TU Kaiserslautern, Germany, in 2014.
From 1996 to 1998, he was with Mitsubishi Semiconductor Europe, Germany, where he was engaged in the design and development of microcontrollers. From 1998 to 2009, he was with Siemens Semiconductor, Infineon Technologies AG and Qimonda AG, Munich, Germany, in DRAM design. During this time frame, he was involved in DRAM design for graphics and commodity DRAM products. In 2006, he was a Design Team Leader for the 1Gb DDR3 DRAM, the first DDR3 volume product at Infineon/Qimonda. Since 2009, he has been with the Microelectronic System Design Research Group, TU Kaiserslautern, Germany. He holds several patents related to DRAMs and DRAM design, and published more than 60 papers. His current research interests include DRAM controller design, Near- & In-Memory processing, 3D-integrated DRAMs, heterogeneous memory architectures, and MPSoCs.