Published a new paper from N.i.P.S Laboratory: Noise limited computational speed, Appl. Phys. Lett. 91, 224104 (2007)
If you want to cite this article, please use the following:
Noise limited computational speed, L. Gammaitoni, Appl. Phys. Lett. 91, 224104 (2007)
L. Gammaitoni
N.i.P.S. Laboratory, Dipartimento di Fisica, Università di Perugia, I-06123 Perugia, Italy and Istituto Nazionale di Fisica Nucleare, Sezione di Perugia, I-06123 Perugia, Italy
In modern transistor based logic gates, the impact of noise on computation has become increasingly relevant since the voltage scaling strategy aimed at decreasing the dissipated power, has increased the probability of error due to the reduced switching threshold voltages. In this paper, we discuss the role of noise in a two state model that mimic the dynamics of standard logic gates and show that the presence of the noise sets a fundamental limit to the computing speed. An optimal idle time interval that minimizes the error probability is derived. ©2007 American Institute of Physics